Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration ("VLSI"). The multilevel interconnections that lie at the heart of this technology require planarization of high aspect ratio apertures, including contacts, vias, lines or other features. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Aluminum (Al) layers formed by chemical vapor deposition ("CVD"), like other CVD processes, provide good conformal aluminum layers, i.e., a uniform thickness layer on the sides and base of the feature, for very small geometries, including sub-half micron (&lt;0.5 .mu.m) apertures, at low temperatures. However, transmission electron microscopy data ("TEM") has revealed that voids exist in many of the CVD formed Al layers within high aspect ratio apertures even though electric tests of these filled apertures do not evidence the existence of this void. If the layer is subsequently processed, the void can result in a defective circuit. Electric conductivity tests do not detect any structural abnormalities. However, despite the generally positive electric conductivity tests, conduction through a contact or via having a void may, over time, compromise the integrity of the integrated circuit devices.
A TEM study of various CVD Al layers formed on substrates indicates that the formation of voids occurs through a key hole process wherein the top portion of an aperture such as a via becomes sealed before the aperture has been entirely filled. Although a thin conformal layer of CVD Al can typically be deposited in high aspect ratio contacts and vias at low temperatures, continued CVD deposition to complete filing of the contacts or vias typically results in the formation of voids therein. Extensive efforts have been focused on elimination of voids in metal layers by modifying CVD processing conditions. However, the results have not yielded a void free structure.
An alternative technique for metallization of high aspect ratio apertures, is hot planarization of aluminum through physical vapor deposition ("PVD"). The first step in this process requires deposition of a thin layer of a refractory metal such as titanium (Ti) on a patterned wafer to form a wetting layer which facilitates flow of the Al during the PVD process. Following deposition of the wetting layer, the next step requires deposition of either (1) a hot PVD Al layer (e.g., about 450.degree. C.) or (2) a cold PVD Al layer (e.g., about room temperature) followed by heating the PVD Al layer (e.g., about 450.degree. C.) to reflow the Al into apertures in the wetting layer. However, PVD Al processes are very sensitive to the quality of the wetting layer, wafer condition, and other processing parameters. Small variations in processing conditions and/or poor coverage of the PVD Ti wetting layer results in incomplete filling of the contacts or vias, thus creating voids. In order to reliably fill the vias and contacts, hot PVD Al processes are performed at temperatures above about 450.degree. C. Because the PVD Ti process provides poor coverage of the sidewalls of high aspect ratio, sub-micron vias, PVD Al does not provide reliable filling of the contacts or vias. Even at higher temperatures, PVD processes may result in a bridging effect whereby the mouth of the contact or via is closed because the deposition layer formed on the top surface of the substrate and the upper walls of the contact or via join before the floor of the contact or via has been completely filled.
A known planarization technology for depositing a PVD aluminum film on a semiconductor wafer 1 is shown in FIG. 1. The semiconductor wafer 1 in the illustration was equipped with the multiple layers of insulating films 4, 5 having a hole 3 on top of the semiconductor substrate 2. Optionally, an electrode wiring (not illustrated) is formed between the multiple layers of the insulating films 4, 5. On the semiconductor wafer 1, Titanium (hereinafter, called "Ti") and titanium nitride (hereinafter, called "TiN") were successively deposited by the sputtering method, which is one PVD (Physical Vapor Deposition) method. By this method, a barrier metal film 6 of Ti or TiN is formed. Next, on top of this barrier metal film 6, a wettability-improving film 7 comprising titanium Ti, which is superior in wettability to aluminum, is formed by the sputtering method, and aluminum 8 is formed into a film at room temperature. Then, by means of applying heat to the semiconductor wafer 1, the aluminum is caused to reflow, or, while the aluminum is being formed into a film by a high-temperature sputtering method, it is made to flow into the hole 3 at the same time. However, with the above-mentioned prior method, the aluminum was not completely imbedded in the inner section of the hole 3, and there was a tendency for an air space to be created in its bottom section. This was because in the sputtering method, the wettability-improving film 7 could not sufficiently cover to the bottommost section of the hole side wall faces. In order to improve the coverage of the wettability-improving film 7 on the hole side wall faces, it is also actually possible to form a film of Ti by means of the CVD method. However, since CVD Ti is generally conducted at a high temperature, this is counter to the preference for low-temperature processes of recent years.
Once a PVD Al layer has been deposited onto the substrate, reflow of the Al may occur by directing ion bombardment towards the substrate itself Bombarding the substrate with ions causes the metal layer formed on the substrate to reflow. This process typically heats the metal layer as a result of the energy created by the plasma and resulting collisions of ions onto the metal layer. The generation of high temperatures of the metal layers formed on the substrate compromises the integrity of devices having sub-half micron geometries. Therefore, heating of the metal layers is disfavored in these applications.
U.S. Pat. No. 5,147,819 ("the '819 patent") discloses a process for filling vias that involves applying a CVD Al layer with a thickness of from 5 percent to 35 percent of the defined contact or via diameter, then applying a sufficiently thick PVD Al layer to achieve a predetermined overall layer thickness. A high energy laser beam is then used to melt the intermixed CVD Al and PVD Al. However, this process requires heating the wafer surface to a temperature no less than 660.degree. C. Such a high temperature is not acceptable for most sub-half micron technology. Furthermore, the use of laser beams scanned over a wafer may affect the reflectivity and uniformity of the metal layer processed therewith.
The '819 patent also discloses that suicide layers and/or barrier metal layers may be deposited onto a wafer before Al is deposited first by a CVD process and then a PVD process. According to the teachings of this reference, these additional underlying layers are desirable to increase electrical conduction and minimize junction spiking.
U.S. Pat. No. 5,250,465 ("the '465 patent") discloses a process similar to the '819 patent using a high energy laser beam to planarize intermixed CVD/PVD metal structures. Alternatively, the '465 patent teaches the application of a PVD Al layer formed at a wafer temperature of about 550.degree. C. However, during the high temperature sputtering process, ion bombardment due to the plasma raises the surface temperature to about 660.degree. C. causing the Al film to melt and planarize. Like the process of the '819 patent, the use of high temperatures is unacceptable for most sub-half micron applications, and particularly for use in filling high aspect ratio sub-half micron contacts and vias. Subjecting wafers to temperatures high enough to melt intermixed CVD/PVD metal layers can compromise the integrity of devices formed on the substrate, in particular where the process is used to planarize a metal layer formed above several other metal and dielectric layers.
Other attempts at planarization of high aspect ratio sub-half micron contacts and vias using known reflow or planarization processes at lower temperatures have resulted in dewetting of the CVD Al from the silicon dioxide (SiO.sub.2) substrate and the formation of discontinuous islands of the CVD Al on the side walls of the vias. The discontinuous islands prevent flow or diffusion of an additional material layer there over, leaving a void in the via. In order for the CVD Al to resist dewetting at lower temperatures, the thickness of the CVD Al has to be several thousand Angstroms (.ANG.). Since ten thousand Angstroms equal one micron, a CVD Al layer of several thousand Angstroms on the walls of a sub-half micron via will completely seal the via and form voids.
Therefore, there remains a need for a low temperature metallization process for filling apertures, particularly high aspect ratio sub-half micron contacts and vias. More particularly, it would be desirable to have a low temperature process for filling such contacts and vias with only a thin CVD layer and allowing the via to then be filled with a PVD metal such as PVD Al.